The present invention relates to non-volatile electronic memories, and in particular, to a method of controlling memory cells in an EEPROM that includes setting a state of the memory cells.
EPROM devices that include floating gate transistors are electrically programmable but are not electrically erasable. These memory devices are erasable only by ultraviolet rays. EPROMs are programmed using a thermal agitation phenomenon in the conduction channel under the effect of a saturation current, which is irreversible.
EEPROMs are electrically programmable and erasable. EEPROMs are programmed or erased by the tunnel effect. The programming and erasing voltages are usually produced by internal circuits of the memory, such as charge pumps or multipliers.
The paper presented by Canet, Bouchakour, Harabech, Boivin, Mirabel and Plossu at the 43rd IEEE symposium on circuits and systems in Lansing, Mich. on Aug. 8-11, 2000 describes an EEPROM cell using a control signal that reduces the electric field of the tunnel oxide during cell programming and erasing.
The paper presented by Canet, Bouchakour, Harabech, Boivin and Mirabel at the ISCAS-IEEE international symposium on circuits and systems in Sydney, Australia describes a control signal enabling a reduction in the programming time. FIGS. 2 and 3 illustrate schematically a memory cell and the voltages applied to its electrodes, respectively during an erasing step and during a programming step. During erasing, the substrate, drain and source are connected to ground, and a positive voltage pulse is applied to the control gate of the memory cell.
The ratio between the floating gate voltage and the control gate voltage is in this case defined by the following formula: Kc=Cpp/(Cpp+Ctun+Cox). Cpp is the coupling capacitance between the control gate and the floating gate, Ctun is the capacitance between the drain and the floating gate, and Cox is the capacitance between the floating gate and the substrate. The tunnel voltage is then defined by Vtun=Kc*Vg, where Vg is the voltage applied to the gate.
During programming, the control gate and the substrate are connected to ground, the source is floating, and a positive voltage pulse is applied to the drain. The ratio between the floating gate voltage and the control gate voltage is in this case defined by the following formula: Kw=Ctun/(Cpp+Ctun+Cox). The tunnel voltage is then defined by Vtun=(1-Kw)*Vd, where Vd is the drain voltage.
These EEPROMs and their control method have drawbacks. To maintain a same injected charge and similar performance, an optimized control signal implies an increase in the drain or gate biasing voltage. It is difficult to devise a power supply for the memory array which generates a sufficiently high biasing voltage. Moreover, this memory cell is subjected to a tunnel effect phenomenon between conduction bands, known under the acronym BTBT, which is the source of an increase in the cell""s consumption. Moreover, the optimized programming and erasing pulses are difficult to generate and complicate the associated power supply.
In view of the foregoing background, an object of the present invention is to provide an EEPROM memory control method and a corresponding EEPROM that overcomes the above described drawbacks.
The method of the invention, which is also in conformance with the generic definition given in the background section, is essentially characterized in that the state setting step comprises a simultaneous application of opposite polarity voltage pulses respectively to the drain and to the control gate of the floating gate transistor. The pulses may exhibit a first portion exhibiting an edge/slope greater than K*8 MV/s, and a second portion exhibiting an edge/slope between K*1 KV/s and K*1 MV/s, with K=1 when the pulse has a positive polarity and with K=xe2x88x921 when the pulse has a negative polarity. The pulses may further have a third portion exhibiting a substantially zero slope, and a fourth portion exhibiting an edge/slope of less than K*16 MV/s.
At least one state setting step may be a programming step in which the voltage applied to the control gate is negative, and the voltage applied to the drain is positive. At least one state setting step may be an erasing step in which the voltage applied to the control gate is positive, and the voltage applied to the drain is negative. The voltages applied simultaneously to the control gate and to the drain may have a same amplitude.
In one embodiment, the transistor is formed in a substrate, and the method further comprises applying the drain voltage to the substrate, at least during the state setting step of the cell. The polarities of the applied voltages may be defined relative to a reference voltage, and the substrate may have a ground whose voltage is the reference voltage. The amplitudes of the applied voltages may be less than 10 volts. The potential difference between the control gate and the drain is between 12 and 16 volts during the simultaneous application of the voltages.
The cell may additionally include a selection transistor whose source is connected to the drain of the floating gate transistor, and a voltage of less than 12 volts may be applied to the gate of the selection transistor during the programming or erasing step of the cell. The voltage applied to the drain of the selection transistor may exhibit the same polarity as the voltage applied to the drain of floating gate transistor during the state setting step.
The invention also relates to an electronic device comprising at least one EEPROM memory cell and a power supply for the cell for implementing the above-described method. The electronic device may be produced on a P-type substrate. The cell may include a floating gate transistor produced on the surface of a P-type well. The electronic device may also have an N-type isolation well separating the P-type well from the P-type substrate.